Storage capacity for two-dimensional non-volatile memory is limited by the area of a non-volatile memory die. Capacity may be increased by making individual memory cells smaller and closer together within the die area. However, decreasing feature sizes for memory cells may decrease reliability, or disproportionately increase costs. Three-dimensional non-volatile memory provides high capacity and high reliability by stacking layers of memory cells. Connections between layers of memory cells and peripheral circuitry above, below, and/or at the sides of a three-dimensional memory array may be routed through additional metal interconnect layers. However, the number of metal interconnect layers above and/or below a three-dimensional memory array may be small compared to the number of layers of memory cells in the array, so routing within the metal interconnect layers may be dense and complex.